1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to a CMOS (complementary metal-oxide semiconductor) type semiconductor device that has an improved performance while maintaining its miniaturization.
2. Description of the Prior Art
In general, a CMOS inverter circuit has a configuration as shown in FIG. 6. Specifically, a P channel MOSFET 60 and an N channel MOSFET 61 are connected in series with respect to a power source VDD and ground. Further, these MOSFETs 60 and 61 are connected in parallel with respect to an input terminal IN and an output terminal OUT. The CMOS inverter circuit of FIG. 6 is usually incorporated into a semiconductor integrated circuit (IC), as shown in FIG. 7. In FIG. 7, a P channel MOSFET 60 and an N channel MOSFET 61 are formed on the same semiconductor substrate. Two MOSFETs 60 and 61 are laterally formed adjoining to each other. This configuration interferes with miniaturization to higher densities in the design of CMOS inverter circuits.
To eliminate the above-described disadvantages, a CMOS inverter circuit as shown in FIGS. 8a, 8b and 8c has been disclosed. FIG. 8a is a plan view illustrating a CMOS inverter circuit. In FIG. 8a, an N channel MOSFET 81 and a P channel MOSFET 82 are formed to intersect perpendicularly with each other. A gate portion 80 serves both as a gate of the N channel MOSFET 81 and a gate of the P channel MOSFET 82. FIG. 8b is a cross-sectional view taken along line A--A of FIG. 8a, illustrating the N channel MOSFET 81. FIG. 8c is a cross-sectional view taken along line B--B of FIG. 8a, illustrating the P channel MOSFET 82.
In FIG. 8b, a P type silicon film 88 having a low-impurity concentration is formed on an insulating substrate 87 made of sapphire. A channel, which will be later described, is formed in the silicon film 88. A silicon oxide film 89 is provided surrounding the silicon film 88 so as to achieve isolation between elements. The gate portion 80 comprises a gate electrode 80a and a gate-insulating film 80b.
The N channel MOSFET 81 has an N.sup.+ type source region 83 and an N.sup.+ type drain region 84. The source and drain regions 83 and 84 are formed on the surface of the silicon film 88 adjoining the gate portion 80. In FIG. 8c, the P channel MOSFET 82 has a P.sup.+ type source region 85 and a P.sup.+ type drain region 86. The source and drain regions 85 and 86 are formed on the surface of the silicon film 88 adjoining the gate portion 80.
In the above-described CMOS inverter circuit, the channel of the N channel MOSFET 81 is constituted by an inversion layer 91 formed on the surface of the silicon film 88 adjoining the gate-insulating film 80b. Further, the channel is within a depletion layer 90 which spreads in the direction from the gate portion 80 into the silicon film 88. On the other hand, the channel of the P channel MOSFET 82 is within the silicon film 88, and is constituted by a neutral region 92 developed between the depletion layer 90 and the insulating substrate 87. Thus, in the P channel MOSFET 82, positive holes, i.e., carriers move from the source region 85 to the drain region 86 by way of the neutral region 92. Therefore, the conductance and the threshold value of the P channel MOSFET 82 are very dependent on the variations in the thickness of both the silicon film 88 and the depletion layer 90.
FIGS. 9a and 9b schematically illustrate the states of channel formation of the above-described P channel MOSFET 82. FIG. 9a shows the state in the case of a gate voltage Vg&lt;Vthp, and FIG. 9b shows the state in the case of a gate voltage Vg=Vthp (threshold voltage). Specifically, when Vg&lt;Vthp (FIG. 9a), the conductance of the P channel MOSFET 82 is in proportion to the thickness (T-W) of the neutral region 92. This thickness (T-W) is the difference between the thickness T of the silicon film 88 and the thickness W of the depletion layer 90. As the gate voltage Vg is increased, the depletion layer 90 spreads, causing the neutral region 92 to be thinner. Finally, the neutral region 92 disappears, and the thickness W of the depletion layer 90 becomes equal to the thickness T of the silicon film 88. As that point, the gate voltage Vg has reached the threshold voltage Vth. As described above, the threshold voltage Vth is very dependent on the thickness T of the silicon film 88.
Therefore, the spread of the depletion layer and the thickness of the silicon film must be accurately controlled to obtain the prescribed conductance and threshold value of the P channel MOSFET. However, it is difficult to precisely control the thickness of an silicon film. In particular, it is extremely difficult to control the thickness of a silicon film when it is being formed on an insulating substrate made of materials such as sapphire.